1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a circuit that operates in synchronization with a clock signal.
2. Description of the Background Art
A synchronous semiconductor device has a construction such that a control signal phase-synchronized with a clock signal given from the outside is supplied to a plurality of circuits, for example, output buffers. In such a synchronous semiconductor device, delayed amount of the control signal received by the plurality of circuits often differs in accordance with the arrangement of the circuits. Hitherto, various methods have been proposed so as to supply a phase-synchronized control signal to a plurality of circuits irrespective of the arrangement relationship between a circuit that generates a control signal and the circuits that operate by receiving the control signal.
Many of these are proposals of methods for optimizing the setting of interconnection length or interconnection width, or the way of drawing the interconnection in order to achieve synchronization. Actually, however, correction must often be made to achieve synchronization if synchronization of a signal has not been achieved because delayed amount of the signal in the inside of a sample product of a semiconductor device deviates from an expected value. It is not until a new mask corresponding to the correction is fabricated and a sample product of a semiconductor device is produced again for evaluation thereof that one can confirm whether or not the correction of the delayed amount of the signal has been made correctly or not.
The first factor that causes failure in synchronization of the control signal seems to be due to errors in estimation of load capacitance, interconnection capacitance, interconnection length, and others in a designing stage. The second factor seems to be a so-called production variation such as finishing variations in transistor capability, interconnection resistance, interconnection length, and interconnection width. If such a production variation occurs, one fails to obtain synchronization because the design parameters used in calculating the interconnection delay in the designing stage go wrong.
Further, there are actually a lot of cases in which the factors leading to failure in synchronization increase because an ideal interconnection cannot be drawn owing to the limitation of the arrangement of internal circuits in a chip layout. These shifts in the delay parasitic to the interconnection are called xe2x80x9cskewsxe2x80x9d, and should be compensated for. However, in the designing stage, it is difficult to read an appropriate adjustment value for correcting the delayed amount.
FIG. 14 is a view for describing a conventional technique of designing synchronized circuits. Conventionally, in a synchronized circuit such as shown in FIG. 14, there have been fundamentally two methods for distributing and supplying an output of a clock output circuit 302 to all of synchronized circuits 304, 306, and 308.
The first one is a method, such as disclosed in Japanese Patent Laying-Open No. 07-121261(1995), in which the delayed amount is adjusted for distributing and supplying the output of the clock output circuit 302 to all of the synchronized circuits. In this method, the position of metal interconnections 310 to 316, the position of interconnection branch points, and the interconnection length and interconnection width of each metal interconnection are changed on the basis of the propagation delay time calculated from the characteristics of an output element included in the clock output circuit 302, the load capacitance in the inside of the synchronized circuits 304 to 308, and the interconnection capacitance and interconnection resistance of the metal interconnections 310 to 316. By changing these parameters, the clock skew and the clock propagation delay time have been adjusted.
The second one is a method, such as disclosed in Japanese Patent Laying-Open No. 10-55668(1998), in which the lengths of real interconnections are made equal to each other by inserting a dummy interconnection or the like on a propagation passageway from the clock output circuit 302 to the plurality of synchronized circuits 304 to 308.
Known designing techniques such as described above are of importance in realizing synchronization; however they have been unable to solve the problems with certainty if production variation or estimation error occurs. In other words, in many of the cases in which such a problem occurs, it is not until the mask is corrected and a sample product of a semiconductor device is fabricated again for estimation thereof that one can find whether the problem has been solved or not.
Thus, an object of the present invention is to provide a semiconductor device capable of adjusting delayed amount of a control signal to each synchronized circuit in order to solve with certainty the problems that occur due to production variation or estimation error.
In summary, the present invention is directed to a semiconductor device having a plurality of internal circuits that operate in accordance with a control signal, wherein each of the internal circuits includes an adjusting circuit that receives the control signal to adjust a delay time for output, and a synchronized circuit that operates in accordance with the output of the adjusting circuit.
Therefore, a principal advantage of the present invention lies in that, since a clock adjusting circuit is provided for each synchronized circuit, the phase of the clock signal can be adjusted for each synchronized circuit block if the delay time caused by a clock signal line differs.
The foregoing and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.